Conference paper
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark1
Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Language-Based Technology, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance.
Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler.
The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
| Language: | English |
|---|---|
| Publisher: | OASICS |
| Year: | 2011 |
| Pages: | 11-21 |
| Proceedings: | Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems |
| Journal subtitle: | Ppes’11, March 18, 2011, Grenoble, France |
| ISBN: | 3939897280 and 9783939897286 |
| Types: | Conference paper |
| DOI: | 10.4230/OASIcs.PPES.2011.11 |
| ORCIDs: | Schoeberl, Martin , Probst, Christian W. and Karlsson, Sven |
