Book chapter · Conference paper
A minimal network interface for a simple network-on-chip
Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead.
This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded.
Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.
| Language: | English |
|---|---|
| Publisher: | Springer |
| Year: | 2019 |
| Pages: | 295-307 |
| Proceedings: | 32nd International Conference on Architecture of Computing Systems |
| Series: | Lecture Notes in Computer Science (including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Journal subtitle: | 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings |
| ISBN: | 3030186555 , 3030186563 , 9783030186555 and 9783030186562 |
| ISSN: | 16113349 and 03029743 |
| Types: | Book chapter and Conference paper |
| DOI: | 10.1007/978-3-030-18656-2_22 |
| ORCIDs: | Schoeberl, Martin , Pezzarossa, Luca and Sparsø, Jens |
