Conference paper
Research of PCB Parasitic Inductance in the GaN Transistor Power Loop
Gallium Nitride (GaN) transistor in the high power density converter application is widely researched nowadays. High frequency switching largely reduces the volume of passive components and also leads to challenges in the PCB layout. Parasitic inductance within the critical power loop should be minimized to fully harness the potential of GaN transistor fast switching capability.
This paper provides a numerical method for the power loop inductance quantification. Experimental results on the synchronous buck converter are given to validate the estimation accuracy.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2019 |
| Pages: | 1-5 |
| Proceedings: | IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia 2019 |
| ISBN: | 1728121450 , 1728121469 , 9781728121451 and 9781728121468 |
| Types: | Conference paper |
| DOI: | 10.1109/WiPDAAsia.2019.8760312 |
| ORCIDs: | Sun, Bainan , Zhang, Zhe and Andersen, Michael A. E. |
Conductors DC-DC power convertors GaN Gallium Nitride transistor Gallium nitride III-V semiconductors Inductance Layout Mathematical model Numerical models PCB layout PCB parasitic inductance Transistors field effect transistor switches finite element analysis gallium compounds high power density converter application power loop inductance quantification printed circuit layout switching convertors synchronous buck converter transistor power loop wide band gap semiconductors
