Conference paper
A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers
A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv.
Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC
Language: | English |
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Publisher: | IEEE |
Year: | 2006 |
Pages: | 500-503 |
Proceedings: | The 32nd European Solid-State Circuits Conference |
ISBN: | 1424403022 , 1424403030 , 9781424403028 and 9781424403035 |
ISSN: | 26431319 and 19308833 |
Types: | Conference paper |
DOI: | 10.1109/ESSCIR.2006.307499 |