Report
FPGA Acceleration by Dynamically-Loaded Hardware Libraries
Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator.
Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs.
Language: | English |
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Publisher: | Technical University of Denmark |
Year: | 2016 |
Series: | Dtu Compute Technical Report-2016 |
ISSN: | 16012321 |
Types: | Report |
ORCIDs: | Nannarelli, Alberto |