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Report

Implementation of Hardware Accelerators on Zynq

Supervised by Nannarelli, Alberto1,2

From

Department of Applied Mathematics and Computer Science, Technical University of Denmark1

Embedded Systems Engineering, Department of Applied Mathematics and Computer Science, Technical University of Denmark2

In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers.

In this work, two different hardware accelerators were implemented on a Xilinx Zynq SoC platform mounted on the ZedBoard platform. The two accelerators are based on two different benchmarks, a Monte Carlo simulation of European stock options and a Telco telephone billing application. Each of the accelerators test different aspects of the Zynq platform in terms of floating-point and binary coded decimal processing speed.

The two accelerators are compared with the performance of the ARM Cortex-9 processor featured on the Zynq SoC, with regard to execution time, power dissipation and energy consumption. The implementation of the hardware accelerators were successful. Use of the Monte Carlo processor resulted in a significant increase in performance.

The Telco hardware accelerator showed a very high increase in performance over the ARM-processor.

Language: English
Publisher: Technical University of Denmark
Year: 2016
Series: Dtu Compute Technical Report-2016
ISSN: 16012321
Types: Report
ORCIDs: Toft, Jakob Kenn and Nannarelli, Alberto

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